Hi everyone. Thank you for joining Teledyne LeCroy today for our webinar with Eric Bogatin, titled "Practical On-die Power Integrity Measurements."



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So, for those of you just logging in, thank you for joining Teledyne LeCroy today for our webinar on "Practical On-die Power Integrity Measurements" with Eric Bogatin.



This is the final session in our new eight-part series on power integrity measurements.



Eric will advise how you can access all eight webinars in a few minutes. So a little bit about us. LeCroy was founded by Alabama native Walter LeCroy in 1964. Our corporate headquarters is located in Chestnut Ridge, New York. But we have sales and service offices all across the United States as well as the rest of the world.



We started as an oscilloscope manufacturer focusing on physical layer tests and have branched out into protocol analysis through several compatible acquisitions.



In 2012, LeCroy was acquired by Teledyne Technologies and renamed Teledyne LeCroy.



A little bit about our presenter, Professor Bogatin founded Bogatin Enterprises in 1992, which we then acquired in 2011.



He has produced over 200 hours of training material for the Teledyne LeCroy Signal Integrity Academy and written more than 18 books.



Eric teaches at the University of Colorado in Boulder for the Department of Electrical and Computer Engineering and currently holds the position of technical editor for the Signal Integrity Journal. We know that there are a lot of demands on your time. We appreciate you joining us today. I'll now turn things over to Eric to begin.



Well, thank you for that introduction.



In today's webinar, I'm going to cover practical on-die power integrity measurements. There's a lot more that I have to talk about than I have time for today, and so I want to direct you to a number of resources.



First is, I've written a number of books that are related to this topic. One of the last ones I did with my buddy Larry Smith is specifically about designing the power distribution network. And a number of the examples I'm going to show you today are taken from this textbook. So I certainly recommend you check out that textbook. And, of course, my other textbook on signal and power integrity, we have a chapter in there specifically about power integrity design. And the last two books that I've done with Artech, the last one that's about prototype breadboard and PCB design, I cover quite extensively in there topics related to reducing switching noise in the design of the interconnects.



And some of the examples that I show in that textbook, I've got some of those circuit boards, and we're going to look at examples from those boards in today's webinar. Now in addition, this is kind of the caboose of a series of eight different webinars that are focusing specifically on mastering power integrity measurements.



So I'd recommend you check out some of the other webinars in the series if you haven't already. And in the PDF copy of these notes, this is a hot link that will take you to that landing page directly.



And, of course, if you're interested in power integrity, be sure to check out our landing page specifically about power integrity. And this covers all of our solutions for analyzing and measuring and suggestions for design principles about power integrity.



And so if you visit our homepage, you'll see a lot of additional information, and there's a link to all the on-demand webinars that cover this topic. And so there's a lot of additional information available for everyone if power integrity is an important topic for you. Well, in today's webinar, I'm going to cover a little introduction to what I think is putting power integrity into perspective. And it's very fitting since this is the last webinar in this series.



It's going to review a little bit about some of the specific issues about designing power integrity and, in particular, measuring some of the important problems related to power rails. And then we're going to look at a couple of tricks I'm going to introduce you to of how we can actually measure the voltage on the die, on the power rails on the die. And we'll see how important it is to look on the die compared to traditional measurements looking on the board itself. And one of those measurements that we're going to run on the die is what's sometimes referred to as rail compression.



And this is looking at the voltage difference between the VDD and the VSS on the die itself. I'm going to show you how we can actually measure that from looking on the board.



And then I'll show you a brief example of the impact of the location of the decoupling capacitor and how the noise on the die when IOs switch is strongly influenced by the location of the decoupling capacitor. And this is a great illustration to really cement that sense of how important the mounting inductance and the loop inductance from the pads of the IC are to where that decoupling capacitor are located.



And then finally, we'll look at one example of the noise we'll see on-die when the noise is coming from the board, when the board is the aggressor.



So let's get started. And by way of introduction, I want to give you a little sense of what I think of as power integrity and why I think power integrity is such a confusing topic. When we talk about power integrity, we're all familiar with the case of utility distribution for power, that we have generators to generate the power. It's distributed through all the overhead power cables, and then we consume it somewhere.



These are the three chief components of any power distribution network. And, of course, this is from utility power, but exactly the same structure and architecture is used on board-level power as well. We've got some sort of voltage regulator module that's generating the power. We get some distribution network on the circuit board with all the additional components, the passive components on the circuit board.



And then we have the consumers that are using that power and converting that into useful information processing or some other function. So it's the same elements. And it's important to keep these three different elements in mind. They all comprise the power distribution network.



I think given that perspective, the reason that power integrity is such a confusing topic is because there's not one problem associated with power integrity. There are many problems.



And it's kind of like the story of the five blind people describing an elephant, that they're each touching a different piece of the elephant and they each think an elephant is a specific part related to what they're touching. And so based on the descriptions each of the different people have, their composite view of an elephant doesn't really look much like an elephant. And I think this is the same thing going on when it comes to engineers describing power integrity, that each engineer touches a different piece of the power distribution network in a system, and they think power integrity is related to what they're looking at specifically.



And so what is an elephant or what is power integrity? Well, it depends on the question you're asking. It depends on what's important to you. Is it related to the VRM?



Is it related to the decoupling capacitors? Is it the cavity noise? Is it the IOs? Is it the noise on the sensitive voltage sources?



And because there are so many different aspects of power integrity and so many different problems involved in power integrity, it's impossible to have one solution that's going to satisfy all of the different problems in a power distribution network.



And so here are those elements we talked about. This is the voltage regulator module where the power is generated. Here's the distribution network. And then here is the consumer.



Now there are a couple of ways of looking at the power distribution network. And I wanted to highlight this because, as we said in the beginning, the problems you care about depend on your perspective.



When Larry and I worked on our book, we took the view from the die's perspective.



And Larry has a lot of experience at silicon design and optimizing the power distribution network for the dies themselves. And so our book focused on the kind of problems that the die experiences and what you want to do to fix those problems. And so our perspective in this textbook that we wrote is really looking over here and looking outward.



But that's not the only perspective that's important. My buddy Steve Sandler, he has a book out called Power Integrity, and his perspective is closer to the VRM. He's looking at what do you need in order to optimize the design of the VRM and the environment it sees into the power distribution network. And so depending on which is important to you, you're going to look from one end to the other.



But it's really about the whole thing. And so I recommend the book that Larry and I did. And, of course, my buddy Steve Sandler's book as well. They're very good resources.



But, again, different perspectives.



But here is what I sometimes use the phrase, it's a strategically simplified model. It is a model that is simple enough in order to understand and work with, but yet still has valuable strategic information in it about how the system behaves. And so here's what we've got. We've got the VRM over here, which I've modeled as a voltage source and the kind of the source impedance, the Thevenin resistance, and kind of an effective output inductance that's related to any filter inductor that's there, plus the feedback loop of the VRM axis.



It behaves like an inductor element.



There's the bulk capacitor on one end. That's where the VRM is. And then on the other end, here's where the power is being consumed. Here's a current source as a simple way of modeling the current draw from the device from the die.



There's some on-die capacitance, maybe a little bit of spreading resistance on the die to distribute that power to the places on the die that need it. And then there's connection from the package to the MLCC capacitors and their model, and then the connection from the decoupling capacitors back to the bulk capacitors on the other end. So here is a simplified model that illustrates the important features of the VRM. And generally, the bulk capacitance over here as from the VRM getting closer to the die, it's always going to be larger, the closer to the VRM we are.



And while as the inductance is going to be smaller, the closer we are to the die itself. So with this perspective, now we can think about some of the problems in power distribution design.



And here I have that same diagram here now from the die's perspective and the VRM's perspective. And now we're going to look at a couple of examples of some of the problems we can encounter and what features in this power distribution network influence that noise. And it all depends on the noise that we see and the problems that we see depend on where we do the measurement in that system and who is the aggressor creating the noise and who is the victim that is sensitive to the noise. And let me give you a couple of quick examples. We're not going to spend a lot of time on this, but this literally is everything you need to know about the power distribution network in order to understand most of the problems that can arise. So when the IOs switch and we're looking at the IO rail, the VCC rail on the die, well, we're going to have current flowing through the IOs off the die.



And generally, the capacitance of the power rail for the IOs, generally, that capacitance is pretty small.



And we have maybe a little bit of spreading resistance, but we have the connection to the local decoupling capacitors. And when we have IOs that switch and we have a large dI/dt, well, that current, that large dI/dt, is going to flow through any inductance in that power distribution network. And of course, when we have a dI/dt through an inductor, we get a voltage drop. So that means the voltage over here, that's the rigidly fixed voltage based on the VRM, that voltage that's fixed over here, when we have a dI/dt, we're going to find this point over here is pretty well linked or anchored by the capacitance. It's this voltage here that's going to change then because of the dI/dt. And if we want to minimize that voltage drop across that inductor, the way we do that is with low inductance.



And effectively, the MLCC capacitor is acting as a local VRM, a local charge storage reservoir from which we're going to draw the current during the rising edge, during the dI/dt time. All that current is going to come from this location here. And so all of this, all of this inductance here is completely irrelevant to the switching noise of this current because all the current is coming from this location, this is the only term that's important. It's only this inductance from the die itself to the MLCC capacitors, providing, of course, we have enough capacitance here to provide the storage during the rising edge.



So one source of noise, the kind of self-aggression noise from the IO switching, when these guys switch, the root cause of the problem is their dI/dt through this inductance. The solution is it's about reducing this inductance. That means using capacitors that are in close proximity to the die and minimizing that inductance, minimizing their inductance. And making sure we have enough capacitance.



It's not about throwing more capacitance at the problem. That's not going to fix or reduce the dI/dt as long as we have the minimum amount. It's going to be about using low mounting inductance. And I'll show you an example of that in a moment.



Another case, suppose this isn't the IO, but it's the core that's switching. And in the core switching, the on-die capacitance can be really large. And now we have another problem, a different problem. When the core logic switches, it's not going off the die, it's staying on-die.



But we want a low impedance in the power distribution map. And looking backward between the pads on the die, between the VDD and the VSS on the die, we want to see a low impedance looking backward so that when that current flows through the PDN, we get a low voltage drop. Well, as soon as we look back toward the rest of the system, we see the large on-die capacitance. We see the package lead inductance that makes a parallel LC circuit.



And that parallel circuit is going to have a peak impedance.



And our goal in optimizing the power distribution network for the core logic switching because of the much larger on-die capacitance that the core logic sees, our goal is to reduce the peak of that large parallel resonance. And that's a different set of design guidelines than just minimizing this inductance. Yeah. It goes a long way toward minimizing the inductance.



That will help. But the other thing that we want to do in addition to minimizing this inductance is we want to damp out that peak. We want the impedance of this network right here where that transient current is going to flow. We want that network to look like a flat impedance, a resistive impedance so that we don't have a peak.



And so that is a different set of design principles than if we're worried about the IO. And then, for example, suppose that we have noise over here. We have noise on the board. And we have not a lot of IO switching.



But we have a device that's very sensitive to noise on the VRM, like a PLL or an oscillator or an ADC or a DAC, some component where we need a very low amount of voltage noise on the power rail, we're not going to have a lot of current switching. The self-aggression noise isn't very extensive, but it's the noise from the rest of the VRM getting onto that device. And in that case, we want to engineer the power distribution network as a filter. We want to filter the noise that's generated over here or over here.



We want to filter that by the time it gets over here on the die. A completely different problem than we had before. And that's why sometimes it's appropriate to use a larger amount of inductance between the source of the noise and using either the on-die capacitance or using the MLCC capacitor. We want a large amount of inductance there.



That's where we use ferrites in order to filter out the noise from getting from over here onto the rest of the network to the die. A complete different problem that we're trying to solve. And so this is just a very brief example of a couple of different kinds of problems that we want to identify where we can use this model. And the model tells us there are different features in the power distribution network depending on the problem we're trying to solve.



Well, in the textbook that Larry and I put together, we have an illustration to identify if you know ahead of time that you want to measure the voltage on the die. You can instrument the package the die goes on and, of course, the board in order to do that. But it's only if you know ahead of time. You have to engineer the features in the package to connect what we call sense lines from the power distribution on the die through the packages, just pass-throughs through the package, and then pass-throughs through the circuit board so we can measure the voltage on the bottom of the board of the voltage on the die.



That means we cannot connect those pass-through sense lines in the package to the power distribution network in the package. They have to be isolated. In order to measure the voltage on the die, we need these isolated pass-throughs in the package. And then in the board, we need to connect them to the pads that we can then probe.



And we can measure the voltage between the VDD and VSS on the die. We can measure that with a probe coming off the board. And if we're doing single-ended measurements, then we're always going to be and we'll see this as a very important feature. If we do single-ended measurements, we're always going to be measuring the voltage on some pad relative to the local ground on the board.



And so we need to be able to measure the VSS line on the die compared to a local pad on the board or the VDD line on the die compared to a local pad on the board, for example, as we're doing over here. If we want to measure the voltage of the rail between the VSS and VDD, that rail compression, then we're going to measure the VSS on the die relative to the board, the local ground on the board, the VDD on the die compared to the local ground on the board. And we're going to use the scope to take the difference between them, and that will be the rail compression. And I'm going to show you how we do that. Now, unfortunately, this requires that you have a special custom package that allows you to have pass-throughs on the die and then a custom board in order to have test points on the bottom of the board. But if you don't have one of these customized engineered packages with pass-throughs, I'm going to show you a trick you can use sometimes.



It's not suitable for all devices, but in some devices. And here's what it is.



It is especially useful if the IO rail, the VCC rail, is shared by the core logic. And that's often the case in a lot of small devices, microcontrollers especially. And here's a very simple, again, a strategically simplified diagram of the IO rail and one of the IOs on one of these devices. So here in blue is the package itself.



This is the off-package components. Here's the VRM. Here's some local decoupling capacitance. Here's the connection, the inductance from the the VRM to the package itself.



Here's the package lead inductance on the VDD and the VSS lines. Here is some of the capacitance on the IO pin. Here's an IO pin coming off. A little bit of capacitance between that IO pin on the die and the high rail and the low rail.



And here are the two gates for a typical kind of CMOS driver. Here's the P-channel. Here's the N-channel. And maybe a little bit of on-die resistance for the distribution of the VSS and the VDD.



And here, I've added a little bit of on-die capacitance associated with that power rail. And if it's an IO rail, this generally is a small amount of capacitance. If it's a core logic rail, this could be as much as 1 µF in some cases.



Okay. So here's the trick that we're going to do.



Assuming that we have a number of IO available, we're going to make a couple of them very important selective IO. We're going to make one of them with its output always pegged low. In other words, if it's an inverting input here, we're going to make the input here high. That'll make the output low. And we're never going to switch that. And if this is a low coming up, that means the N-channel is on, the P-channel is off. So we're going to turn that N-channel on.



The N-channel is effectively an analog switch. It is going to connect the output pin to the VSS rail on the die itself. And that's going to come off through the IO in the package onto the board and we're going to route that over to a test point. And we're going to measure the voltage on that point relative to local ground on the board.



And when this output is low, that means we are literally connected to the VSS rail on the die. And so the voltage here is the voltage on the VSS rail on the die relative to local ground. And in that way, we're going to measure ground bounce voltage on this side. And when we have dI/dTs from other IOs that are switching and they flow through that package lead inductance, that whole package is going to bounce up and down. We're going to see that as the voltage on that quiet low line measured relative to local ground on the board.



And at the same time, on another IO, we're going to peg it as an output high. And so when it's an output high, the P-channel is going to be on and the N-channel is going to be off. And again, this MOSFET is basically an analog switch. It's going to connect the output to the internal VCC or VDD rail on the die.



And so for that IO that's never going to be switching, it's just pegged high. When it's coming off the board or off the package and we measure it over here, we're going to measure this point over here relative to local ground.



We're going to be looking at the voltage on the die at this point through this connection, this sense line, relative to local ground.



Of course, even if this isn't switching, as the the ground rail on the die switches, as this this point here switches and bounces, we'll see it over here. And so this point will have the ground bounce as well as the parallel bounce on it. But the difference between the VDD from a sense line and the VSS from a sense line, the difference will be the compression, will be the voltage difference on the die. So that's the plan that we're going to take.



We're going to use a quiet high and a quiet low. There will be sense lines to bring the on-die VDD or VCC directly to a test point on the board and the VSS on the die to a test point on the board. And in that way, we'll be able to measure what's going on on the die. And, of course, this is only going to work.



We only have the ability to bring a sense line through IOs that are switching. And so if there's a separate core rail over here, we just don't have any way of detecting it. We're not going to be able to see that unless we have an instrumented package. But if the core is shared by the IO rail as it is in a number of microcontrollers, we'll be able to sense the voltage on the die with this method.



And the other thing that we're going to do while we're on the board is we're going to add a little slammer circuit.



And that slammer circuit is going to be just a simple electronic load.



We're going to turn a MOSFET on, and we'll have a little bit of a sense resistor here. We'll turn that MOSFET on, and we'll get some current through that sense resistor.



As the MOSFET draws current on the power rail, we'll see that current draw. We'll measure it. That will be our source of noise on the power rail of the board. And we'll look at that noise on the board, and then we'll see how much of that actually gets to the on-die voltage rail.



And so in that experiment, the power rail on the board will be our aggressor, we'll make some noise there, and we'll look to see how much of that gets onto the die. So that's kind of the plan we're going to do. We're going to instrument a little microcontroller this way. We're going to do some measurements on the board level.



We're going to look at the noise when IOs switch, and we're going to look at noise on the die when there's noise on the board and see how much couples over there. And the the last thing I want to mention is the scope that we're using today. This is really my favorite scope. This is my workhorse scope that I use all the time.



This is the WavePro HD.



I've got four channels on it. It's an 8 GHz bandwidth for each of the channels. Each channel has 12-bit vertical resolution. And I have the capability on two channels at a time to look at 20 gigasamples/second sample rate, 12-bit vertical resolution. That's every 50 ps, we can take another measurement.



So it's a lot of capability. So we're going to use the scope and a board that I've instrumented with a quiet high and a quiet low. And I'm going to take you into my lab, and we're going to set up the measurement. And we're going to look at the noise on the die when it's sitting in idle state.



So let's take a look at a couple of the examples. We're going to look at idle state when just one of the IOs is triggering, and we will be able to use that IO to trigger the scope. And we'll look at the on-die noise, and we'll see that we can get a good measure of some of the clock edge noise on the die in this case. And then we'll look at rail compression.



We'll turn on some more IOs. We have a lot of current that's switching. We'll look at some of the switching noise there.



And then, maybe we'll also look at the impact of the decoupling capacitors at that time on another board. And then we'll look at the case where we drive noise on the board, the board rail, and how much of that board rail noise gets onto the die itself. We'll look at this idea of rail compression. So with that, let me bring you into my lab, and we'll do some measurements here to finish off our webinar today.



Hi, guys. I brought you into my lab. I'm going to show you a demonstration of some of the principles we just talked about. I've got a simple microcontroller board here.



This is the microcontroller itself. The rest of these are just kind of fanning out a lot of the IOs to peripheral pins. There's an ATmega328 microcontroller over here and I've written some code in order to drive one of the IOs as a quiet high, one as a quiet low and then we're going to trigger some of the others. Now to make it easier to probe, I built this little shield that fits on top and literally all it's going to do is connect the IO pins over here to various loads and bring out two test points over here so we can measure it.



To start out, I've got the IO switching, one of the IOs switching, and we're going to look at that signal coming out. And you can see here on the board, it's actually running and a little hard to see, but this LED is on just a tiny little bit of the fraction of the time. And when it goes on, we're going to drive current through this little resistor. We can measure the current through it.



But in particular, I'm going to use this as my trigger. We're going to look at this voltage over here with our scope probe. We're going to measure that voltage command. That's we're going to use to trigger the scope and then we're going to look at the line that's being pulled out as a quiet low and a quiet high.



So the quiet low means that output pin over here, the transistor is pegged low. Its output is connected to the VSS rail on the die itself here, and then that pin comes out and comes over here, and we take it off over here with the scope probe. And likewise one of these is pegged high so its output is always high, its output the P-channel is connected to the VDD rail or VCC rail on the die itself and that pin comes out and it's a sense line over here and then we're going to pick it off over here and measure it with our scope. So we're going to trigger the scope on one of the IOs switching.



We're going to measure a pin that's always low and a pin that's always high and we'll look at that voltage noise on the die itself. Now to get started doing that, here's my lab. I've got my scope over here. I'm going to zoom over here.



Here's my scope and a little hard to see. So we're going to use TeamViewer in order to see what's on the screen on my computer. Now we're going to do measurements in a number of channels. And so here's one of the tricks I really like using because we have four different probes we're going to use to keep them straight.



I like using these little color bands that help me keep track of which probe is connected where and what is it displaying. And you notice the color code I use. It's no coincidence that when we look at the signals on the scope itself, hard to see the colors here on the side, that channel 1 is yellow, channel 2 is red, channel 3 is blue, and channel 4 is green. And darned if that doesn't match the color code that we see over here.



And when we come over here and we probe our board, when we probe our board, we're going to be consistent and use the same color coding on the end of the probe so we know exactly which channel we're going to display where. So let's get started. We're going to take a look at channel 1 first.



And channel 1 is going to be the trigger to the scope. That's going to be the IO switching. Now, again, remember Rule #9. Before you do a measurement, anticipate what we expect to see.



So this is going to be one of the IOs switching. That's going to be 0 V to 5 V. It's going to turn on, about 4 ns or 5 ns or so. Pretty fast edge.



And so here it is. So let's look at channel 1 and notice the yellow band over here.



This is going to be on channel 1 on the scope and we're going to see our 0 V to 5 V signal and sure enough here we are and you can see on this scale. It's about 3 µs on time here at 0 V to 5 V, exactly as we expected to see.



And I'm going to zoom in on that edge. Let's see what the rise time is. And so, let's see. I'm going to come over here and we're going to zoom in on that edge. We're triggering, so make sure we're triggering on channel 1 over here, and we're triggering on the rising edge.



Now let's change that time base and really zoom in, and there we go. Okay, so there's the edge. Now, again, part of situational awareness, think about the rising edge, think about the sample rate. We're at 20 gigasamples/second, every 50 ps.



We're taking a measurement, and we're at 5 ns. So we have 100 measurements per division here. Plenty of resolution to see that edge. And it's on the order of about a division here.



I can read it right off the front screen. But if we want to get a little bit better value, we can get the 10-90% using a measurement function. So I'm going to turn on a measurement function. I'm going to turn on my measurements.



You can set up different values. And, let's see. I like statistics, so I'm going to turn on, statistics is already on this. Great.



And now for the first measurement, I want to know what's the 10-90% rise time. So I'm going to come over here, just highlight this, going to bring up the first measurement or first parameter. Oh, it's already selected for rise time. I could have gone here and say that's a horizontal measurement, and I want let's see, where's rise time here?



Yeah. Here's rise time. Okay. Set up rise time. I want channel 1, and there it is.



And so that's how we're measuring it, the 10-90% rise time. And then this is what we're measuring, and here's the average value. 4.7 ns is the rise time. The bandwidth is a little bit under 100 MHz.



And so again situational awareness, bandwidth of signals under 100 MHz. The probe bandwidth is a couple hundred MHz. The scope bandwidth is 8 GHz. I got plenty of bandwidth to see the real signal.



So everything should be looking pretty good. So I've got a good measure of the rise time of that signal. Okay. And I'm going to turn off the parameter so it's not in the way anymore.



We got a little bit more room available for us on the screen. And now let's take a look at the noise.



So here's my setup. Let's look at the quiet low. So we're going to look at the VSS rail on the die, on this die here. We're going to look at that VSS rail relative to the local ground on this board here, which is connected through one of the pins to the local ground on this board over here.



So I'm going to grab channel 2, which is red. I'm going to get my red probe, and I'm going to come over here. I'm going to measure the quiet low. So what do we expect to see?



It should be 0 V, but we're going to see a little bit of signal on that edge. Now you'll notice my probes I'm using on the probe. I'm using that little ground spring tip for two reasons. One is it reduces the inductance in the tip that gives us a higher bandwidth less distortion of that signal but more importantly less crosstalk between the probes when I have them close together and I'm looking at low-level signals so and I've designed test points on the on the board in order to be able to insert get the test points on the board in order to be able to just insert the probe and its adjacent spring tip so that we can do a high-bandwidth measurement as well.



So let's get the probe in there and when we got it in there, look it's self-supporting. So it's a hands-off kind of operation. Very, very convenient. Okay.



So now let's look at that signal. It should be close to 0 V. Let's look at it on the scope. So I'm going to turn on the second channel and I'm going to zoom out so we can see a little bit more of this.



And you'll notice, look, I'm at 0.5 V/div. I can see some noise there. Let me zoom in a little bit.



And here we have 200 mV/div. Not only can you see some noise, but look, it's stationary, synchronous with respect to the edge.



And what's the period of it? Let's see. From here to here is a fraction of a division here. It's 50 ns/div.



So maybe this is about 30 ns, the period between these. That makes the frequency 1 over 30 is about 32 MHz, 33 MHz. That's twice the clock frequency. What we're seeing here when we look at the quiet low is noise that's synchronous with both edges of the clock.



There's a slightly different pattern to them, a slightly different current waveform that's going through that dI/dt going through the low inductance side. This is clock edge noise. This is the ground bounce, the voltage noise on the VSS rail relative to the board rail, board ground. This is the noise on the VSS on the die that we see as synchronous with the clock.



This is giving us a little measure of the heartbeat on the device. And you can see right over here where the IO turns on, we get a little bit of current, we get a little bit of a dip here. The voltage is negative when we have the dI/dt increasing, kind of as we would expect on the low for ground bounce. We covered this in one of the previous webinars looking at this kind of voltage noise.



While we're here, let's look at the falling edge. This is the rising edge. So I come over to the trigger. I change the trigger.



We look at the falling edge. There's the falling edge, and sure enough, instead of going down, it's going up exactly as we would expect. We have the same clock edge noise, same synchronous with this edge because this is driven by the clock edge, and we see a little tiny bit of the ground bounce noise.



This is the voltage on the VSS relative to the board-level ground over here. So now let's look at the voltage on the VDD rail. So I'm going to use another probe for that. Let's see. Let's see my turquoise probe so here it is. And we're going to measure the voltage on the high side. And what's it going to be? Not only it's going to be about 5 V, but we ought to see a little bit of noise on top of that. So let's come in here.



There we go. We got in contact there. Now let's turn on channel 3.



So here's channel 3. Hey, sure enough. Look, here's 0. Here's our 5 V. Now that's a pretty nice looking 5 V rail on the die itself. But if you look closely you can see just the purest hint of a little bit of clock edge noise.



In order to see that more clearly, let's zoom in on the scale and to do that I want to center that signal in the center of the scope so that when we change the scale, when we expand the voltage scale, it expands about the center. So we highlight the channel and now I'm going to we've got it zeroed already, and now I'm going to zoom in on that scale. And I want them on the same scale. Here we are, 200 mV/div.



And look at that. You can see that clock edge noise. I'm going to move it up just to make it a little bit more clear. And you know what?



We don't need the trigger here. I'm going to move the trigger to the other side. Here is the VSS noise. And let's see, where's ground? There's ground.



There's 0 V anyway. And this is the VSS noise. And here is the VDD noise. And you can see that there's a definite connection between these.



They're not exactly the same. Some of this voltage remember this is the voltage I'm measuring on the sense line that's going to the VDD rail on the die relative to the board ground. So some of this is probably the ground bounce of the whole package. The whole package and the VSS and the VDD rail are both going up.



Some amount of that related to this much voltage noise. This is the total voltage noise I see on the die's VDD rail plus any of the the package bouncing, I really want to see what's the difference. What is the voltage rail collapse on that power rail on the die? And to do that, I really want to see the difference between these.



So let's see how we can do that. I want to create a math function that will display the voltage difference between the VDD on-die relative to the board ground and the VSS on-die relative to the board ground and take the difference. That way, the board ground and the stuff going on up to the package, I'm not going to see. I'm just going to see the rail collapse on the die.



So I'm going to add a math function here, and that math function, we'll put it over here, that math function, I want it to be the difference voltage. So I want a really simple relationship. I want basic math. I want a difference between two channels. And here I have my options.



I want the voltage on rail 3, here's channel 3, minus the voltage on channel 2. That's the difference. That's what I want to display.



I'm going to put it over here, and I want it on the same scale. So I want it on 200 mV/div.



And there we are. Now we're cooking.



Now we've got the voltage on the VSS relative to the local board ground, the voltage on the VDD relative to local board ground, and this is the rail collapse on the die. And you can see very clearly that clock edge noise.



And you can see that it's pretty darn constant voltage except for the clock edge noise. We're looking at the rising edge. We see a little bit of voltage drop here. But you know what? I'm not sure I see a whole lot of the rail collapse when that one IO switches. Let's see what happens when we look at the falling edge. So we change our trigger to the falling edge.



And now you can see when I have a release, yeah, I have a little bit of ground bounce here. I have a little bit of voltage noise on the power. But look, here is the release on that power. This is the rail collapse noise again. Not very much on this scale, 200 mV, but I only have one IO switching now before we make any other changes. Let's add one more trace. This is the voltage on the die.



This is on the power rail. This is on the ground where this is the rail collapse, or the compression, the rail compression between the VDD and VSS. Let's look at the voltage noise on the board. On this board, I've instrumented my little shield here with a connection to the 5 V rail that's on the board level.



So the power is coming in from the USB over here. That's coming ultimately from my computer in this case. Pretty stable voltage source. That's powering voltage distribution on the board and that's coming to this pin over here.



And again, I've instrumented with a voltage probe, a scope probe. I can measure the voltage on the 5 V on the board. And what do we expect to see? It's going to be 5 V as well.



How much of this clock edge noise are we going to see? Remember, this is the noise generated on the die and to get from the die to the board, I've got to go through the package lead. I've got to go through the decoupling capacitors, which are not very well designed on this particular board.



And so I'm going to filter some of this clock edge noise that's on the die by the time it gets onto the board level. And so I might see some of it but not as much of it. Let's see how much we've got. So here is my fourth probe.



And again, you see the importance of using these color bands. This is going to be channel 4, the green band. And I'm going to look at the clock edge noise over here. And you also see another advantage of using this particular kind of footprint for the probes is once I stick the probe in there, it's hands-free.



I can have four probes and I don't need five other people to come over in the lab and help me hold the probes in place. They're all self-standing. So now let's turn on channel 3. So I come over here, and I just highlight the channels.



I can turn on channel 4.



And there's channel 4 over there. I'm going to move it over to this side. Let's see. Channel 4.



I let's see. It's 5 V, but I'm off scale here. So I'm going to change the scale.



There it is. I don't see a whole lot of noise, a really nice looking 5 V rail. I'm going to move it to the center so I can now expand about the center. And now I'm going to expand that scale.



I went on the same 200 mV/div scale. Everybody's on that scale. And now let's move it up here, and we can do a direct 1-to-1 comparison.



So the yellow color here, that is our rail compression on the die. That's the voltage noise between the on-die VCC VSS. And look here in green, this is on the same scale 200 mV/div. That's the voltage noise I've measured on the board.



Perfect example of we're generating the noise on the die. We generate the noise on the die because of the switching IO, again not very much of it, and the clock edge noise. By the time it gets from the die to the board level, it's been filtered with a low-pass filter of the package lead inductance that leads to the traces going to the capacitors and the decoupling capacitors and so I see a much smaller fraction on the board because of that low-pass filter in between them. If I do a measurement on the board and I see the green trace and say oh, that's the voltage noise on the 5 V rail.



It's very misleading thinking that that is all the voltage noise that's on the die itself, and that's what I care about what's going on on the die. Now not a lot of noise in this case so let's get some more of these IOs switching. So I'm going to write the code to drive not one but four IOs switching and I'm going to get a lot more current and let's look to see what happens to our noise sources.



So I've uploaded the code, and I've got many IOs switching. It's a little busy here. Let's see if we can decompose what we're seeing. So we're looking at the falling edge. Let's look at the rising edge.



So here's the rising edge. And now I'm going to move some of these away so we can look at them one at a time and understand what we've got.



So here is that edge that's switching and here is the VSS noise. And you can see, hey, we've got a little bit more VSS noise because we have more dI/dt current with more of those IOs switching. Still not very much in this particular example. It's still on the order of a peak-to-peak maybe 200 mV. Now let's look at the voltage noise on the rail.



So here is the voltage noise on the rail and now you can see we've gotten some more voltage rail collapse over here. We've got the little bit of a DC drop over here. And if I zoom out, let's look at that pattern.



Wow.



So and let's isolate everybody. So we're going to move our trigger over there, we're going to move our VSS over here, and we're just going to look at the pattern. So we see a voltage drop here, which could be mostly the VSS. We'll look at the rail compression, but you notice a little transient response.



We have a DC offset. We draw more current. The voltage rail on the die drops, and that's because of the DC IR drop in the metallization on the die. More current through it, we get a voltage rail collapse compared to when we don't have any current.



And you can see that little bit of transient response here. This is that RLC response of the on-die capacitance, the package lead inductance is that transient response that was here. Damped out because of the very high series on-die resistance here. So this is what's going on on the die.



This is the VSS rail. And now let's look at the rail compression.



And so here is the rail, this is the voltage between the VDD and VSS on the die and you can see that it's a relatively large drop. It's on this scale here. It's about 200 mV, DC drop. That's the IR drop because of the metallization on the die. Now let's look at the release over on the other side. So we'll look at the falling edge, and let's zoom out so we can see that in a little bit more detail.



And let's isolate just the rail compression.



So this is the voltage noise on the the rail itself when the current turns off. Remember this scale, this is 0.5 V/div now. So this is 1, 2, this is almost 1.5 V of voltage noise on the die.



What's going on on the board?



Well, here's the voltage on the board. You hardly see anything. And so in this case when those IOs switch and they release, we're getting that transient response of the power rail, almost 1.5 V of noise on the die when that current turns off. Here's the voltage on the board.



You hardly see any of that noise at the board level. The noise is happening on the die, very little of this high-frequency noise gets onto the board. Let's zoom out a little bit and see if we can see any more of the response on the board. Here's the board response. Here's the on-die response.



And again, we'll move it back to the same scale. They're both on the same scale and you can see that we're sensitive when we look on the noise is happening on the die in this case the noise is happening on the die very little of that noise is actually getting out onto the board. It's all about where the source of the noise is happening, where we're doing the measuring, who's the aggressor, who's the victim, and what that low-pass filter is in between them. Now I want to do one last experiment here for you.



Right now, we're generating the noise on the die and we're looking at the noise on the die, we're looking at the noise on the board, and we see that low-pass filter. Let's go the other way. Let's generate noise on the board, and we'll look to see how much that noise on the board gets on the die.



So on this board here.



I've got on this board a small MOSFET. It's a little slammer circuit. I'm going to draw a current on the board that's going to generate noise on the board and we'll see how much of that noise gets onto the die. So let's upload the code in order to do that.



So I've got the code loaded. We are driving the little MOSFET here. A little hard to see. It's all buried in our probes.



Let's see if we can, there's the MOSFET. We're driving that little guy. He is, and here in yellow, again color coding is so very important. This is the signal that I'm using to drive that MOSFET.



I'm using one of the IOs here to drive that MOSFET. It's a slammer circuit. It's going to turn on and we're going to get current through the resistance. And this is actually a measure of the current through that 10 Ohm resistor.



This is about 400 mA of current that we're getting through the power rail on the board.



And so that little MOSFET is drawing 400 mA of current from the power rail to ground.



And we're looking at that current through that sense resistor. Here it is, let's zoom out. We'll see how long that lasts for.



And here you can see that it is about 400 µs. So the current turns on, it's dropping off, decaying away, and then turns off after 400 µs. So that's the current that we're drawing through the board. Now let's take a look at each of our signals.



So first, let's look at the board-level noise. So this is the voltage on the board. You can see a pretty hefty amount of voltage. Let's see.



It's 200 mV. Let's go to 500 mV.



So here is 500 mV. I'm going to move it up here to the top here. So you can see that, okay, when that current turns on, we get this kind of DC drop. It reaches steady state over here.



This is about the transient response of the power supply, my USB supply that's feeding this. The transient response is changing a little bit because of my computer, but, look, we have 0.5 V/div. Oh my gosh. We have almost a voltage of 1 V drop on that power rail.



Let's zoom in over here at the initial drop.



This is that dI/dt through the inductance of the leads on the board more related to where I'm picking off the voltage that I'm measuring than anything else. But as that current turns on, this is the voltage across the inductance from where I am measuring on the board at this location over here through the pin over to the nearest decoupling capacitor and that decoupling capacitance on the board that's providing the local current. So this is the dI/dt voltage drop. And so when I turn off the current, I ought to see this voltage increase.



So let's check that. Let's go to the, again, consistency test. This is part of situational awareness. And sure enough, when that current turns off, we get the voltage release, the positive voltage across that inductance from where I'm measuring to that other point.



So very consistent. This is all about the dI/dt and kind of the configuration of measuring. This is what's happening on the board. Let's go back to our rising edge.



We're going to zoom out.



And so this long time to discharge, this is the discharging of the decoupling capacitor and ultimately, going to the Thevenin resistance of my power supply. This voltage drop here is the DC voltage because of the Thevenin resistance of the USB hub. And so I'm getting almost a 1 V drop altogether. That's what's going on on the board. Now I'm done with my trigger over here. Now let's take a look at what's going on on the die itself. So here is the voltage on the die. Let's move it to the same voltage scale. It's 0.5 V.



Oh my gosh, I don't know about you, but I can't see a whole lot of difference between these guys.



Here is the voltage noise on the board. Here's the voltage on the die. Absolutely identical because this is really low-frequency stuff. Well, let's take a look at that initial voltage drop that's on the board. Let's zoom way in.



And now we see the voltage noise on the board. This is all throughout the board-level distribution. This is high-frequency noise on the board. Hardly any of that gets over to on the die. That's the blue is on the die. So again, we have the filtering. The noise is happening on the board, little of that is getting onto the die.



Again, where we measure is just as important as who is the aggressor and who is the victim. Let's take a look at the rail collapse. We'll do that on the same scale as well. Here's the rail collapse. See if I can move him on top of it. And again, you can see that we see very little of that voltage noise on the board level generated on the board level that's getting onto the die as rail collapse.



Okay. So let's just take a look at what we've talked about. We've been able to use these sense lines to look at the voltage noise on the die itself. In this particular case, the core logic, the VDD rail, and the IO rail are sharing the same power rail, and so using an IO as a sense line let us see not just what's going on on the IO rail but also on the core logic rail as well.



And that was very fortuitous for us so that by using sense lines, the IOs as sense lines, we're able to probe what goes on on the core logic as well. We can see that clock edge noise. We can see the ground bounce noise. We can see the parallel collapse when we have multiple IOs switching.



We can see the impact of that high-frequency noise on the die. Little of it gets onto the board and likewise, the high-frequency noise on the board, little of that gets onto the die itself. And so I wanted to illustrate this measurement technique and some of the insight we can gain about what's going on on the die using this method. And now let's go back to the slides.



I'm just going to summarize for you what we've talked about. I want to finish up and just summarize some of the things that we've seen in the webinar here today.



One of the most important principles we talked about is this idea that the noise that we measure depends on where we measure it. It depends on where the aggressor is and who's the aggressor and who is the victim.



And in some cases, we saw that the interconnects, the power distribution network acts as a filter between the aggressor and the victim. And sometimes it acts as the self-impedance that we want to engineer in order to minimize the self-aggression noise on the die. So thinking about what is the structure of the PDN, and who is the aggressor, and who is the victim is really important in order for us to understand what elements of the PDN influence the design solution. And we also saw that just because we measure noise on the board level and we see, oh, there's some voltage on the board, doesn't mean that's the voltage that we're going to see on the die. Again, because of the low-pass filter that exists between the location on the board we do the measurement and where we see it on the die.



And generally, obviously, it depends a lot on the specifics. But, a rough rule of thumb, a lot of the power distribution network elements, unless we do something special, their pole frequency is somewhere in the order of 1 MHz or so. Of course, we can move that plus or minus two or three orders of magnitude by engineering, but it's roughly on the order of 1 MHz. That means that noise with frequency components that are less than 1 MHz are in the passband region, and they will generally appear everywhere the same on the power distribution network.



Whereas noise that is higher than 100 MHz is going to be very localized and is not going to transfer between locations. And of course, that's how we engineer the power distribution network. And that's one of the ways in which we minimize the noise in the power distribution network is we make that pole frequency as low as we can so that noise in one location doesn't get to noise at another location. Well, in this webinar, we've covered a lot of ground, but there's still plenty more in order to discuss. And so I want to, again, remind you of a couple of important resources available to you. You want to check out the information about the scopes that we used and some of the probe technology. And, of course, check out some of the lectures that we have on the Signal Integrity Academy.



And, if you find this topic of power integrity is really important for you, then you'll definitely want to visit our landing page. We'll learn more about some of the solutions we offer to solve power integrity problems and to measure some of these power integrity effects.



And be sure to check out some of the additional webinars that we have available specifically on this topic that are linked from the power integrity page. And then generally, some of you have been joining us for our webinar series for the last couple years. We have a gazillion different webinars on a variety of topics related to measuring important signal and power integrity and EMI kinds of issues, and using measurements to help identify the root cause of problems, and check for compliance. And so I want to invite you to be sure to visit our landing page with all of the on-demand webinars we've done in the past, and be sure to join us for some of our future coming webinars as well.



And then finally, you can download a copy of MAUI Studio, which is basically the software that runs on our scopes that is available to you on your PC so you can evaluate some of the tools. And more importantly, you can analyze some of the measurements you took on a scope, offline directly on your PC.



And so with that, I'm going to throw the floor open for questions. And thank you all very much for joining us today, and I look forward to seeing you guys someday in person when we're back to normal and otherwise, on our next webinar.